Frequency synthesizers are well known in the electronic art. A desirable characteristic of a frequency synthesizer is its ability to provide a stable output frequency across a range, or band, of frequencies. Stable frequency generation is typically accomplished by using a so called phase-locked loop (PLL).
FIG. 1 depicts a simplified schematic diagram of a prior art PLL frequency synthesizer (10). The PLL synthesizer (10) includes a voltage controlled oscillator (VCO) (20), the output frequency of which can be adjusted by an input control voltage. A phase detector (40) compares the output frequency of the signal from the VCO (20) against a reference signal (30) and produces, at an output port of the phase detector (46), a control signal that is related to or derived from the phase difference between the VCO (20) signal and the reference signal (30).
A low-pass filter (50) coupled to the output of the phase detector (40) produces a relatively slowly changing (sometimes near D.C.) control signal, typically having a predetermined magnitude and polarity, that when input to the control input of the VCO (20), causes the VCO output signal to match the phase and therefore frequency of the reference signal (30). If for example, the output frequency of the VCO (20) is initially at some frequency f.sub.1 (as it is depicted in FIG. 1A), and if at this same particular instant in time the output of the reference signal source (30) is at a slightly different frequency f.sub.2 (as it is depicted in FIG. 1B, where f.sub.2 .apprxeq.f.sub.1 +.DELTA..phi., and where .DELTA..phi. might be positive or negative), these two signals, f.sub.1 and f.sub.2 at this particular time will differ by some phase angle amount, x.apprxeq..DELTA..phi., if f.sub.1 .apprxeq.f.sub.2. The phase angle difference between f.sub.1 and f.sub.2 will produce an output voltage signal from the phase detector (40) that is a voltage proportional to the magnitude of the phase (or frequency) difference between the two signals, which signal from the phase detector (40) when coupled to the control input of the VCO (20) will cause the frequency of the output signal of the VCO to change toward the frequency of the reference signal (30). As the output frequency of the VCO (20) changes in response to the control signal from the phase detector (40), the phase angle difference between the VCO output signal and the reference signal will decrease. Over time, the phase angle difference between the output of the VCO (20) and the reference signal (30) will tend to zero, producing a correspondingly decreasing output voltage from the phase detector (40), as indicated in FIG. 1C. In the phase locked loop shown in FIG. 1, the output voltage of the phase detector (40) eventually reaches zero, as shown in FIG. 1C, as the frequency of the VCO changes to identically match the output frequency of the reference signal (30).
In many communications applications, a frequency synthesizer must be very stable. In many of these applications, the output frequency for the synthesizer must be changeable in very small, incremental steps. The output frequency of the synthesizer shown in FIG. 1 can be made changeable by discrete, incremental steps by using a reference frequency source (30) having an output frequency equal to the desired step size and using a changeable frequency divider at the output of the VCO (20) to divide the output frequency of the VCO down to the frequency of the reference signal. In such a circuit, the output frequency of the VCO (20) will change by an amount required to lock its output frequency, divided by the division factor of the frequency divider, to the frequency of the reference signal (30).
In FIG. 2, there is shown a prior art frequency synthesizer (12) that uses a voltage controlled crystal oscillator (21) which has significantly greater frequency stability than other types of oscillator circuits. By means of the programmable divider (25) and a low frequency reference signal (provided by the reference oscillator (30) and a second frequency divider (34) that divides the output of the reference oscillator (30)), the synthesizer shown in FIG. 2 (12) provides an output signal frequency that is changeable in small incremental frequency steps across the frequency range of the VCXO.
In FIG. 2, the voltage controlled crystal oscillator (21) (hereinafter referred to as VCXO) has a nominal crystal resonant frequency of 73.8 MHz. It is well known in the art that this resonant frequency can be pulled slightly using a varactor tuning technique to provide a frequency adjustable between 73.798 and 73.802 MHz. The voltage swing between these two frequencies is accomplished by means of a control voltage derived from the phase difference between the signals input to the phase detector (40) i.e. the output of the first divider (25) compared to the output of the second divider (34). The phase detector (40) produces its output control voltage F.sub.corr by comparing the divided-down output frequency of the VCXO (divided by a number between 738,000 and 738,032 in FIG. 2 to yield a signal of approximately 100 Hz.) to the output frequency of the reference frequency signal (30) (also a signal near 100 Hz.).
If the divisors of these two divider circuits (25 and 34) are selected to both produce a resultant quotient that is approximately equal to the frequency step size desired from the synthesizer (a step size of 100 Hz. in FIG. 2), the control signal output from the phase detector (40) as it is filtered by the low-pass filter, will only change the output frequency of the VCO by an amount required to lock the VCO signal to a multiple of the reference signal.
For example, if the VCXO's nominal resonant frequency is 73.8 MHz. and the division factor and the first divider (25) is selected to be a division ratio of 738,000 the product of the division of the VCXO output signal F.sub.out by the divisor factor of the divider (25) will be approximately equal to 100 Hz. If for example the reference frequency (30) is selected to be a reference oscillator of a 7.200 MHz. frequency and if the divisor R in the second divider (34) is selected to be equal to 72,000, the resultant signal from the reference source (30) divided by the division factor in the second divider (34) will also be a signal of approximately 100 Hz.
In a frequency synthesizer such as the one shown in FIG. 2, using a VCXO, (a voltage controlled crystal oscillator) which has a relatively narrow tuning range, very large division factors in the divider (25), will cause the frequency synthesizer (12) to have extremely long lock up times because of the relatively small correction signal from the phase detector (40) and the very narrow tuning range of the VCXO. Long lock up times for a frequency synthesizer render it useless during the time that the VCO output frequency is changing. In a radio using such a synthesizer, the radio would be unusable during the time that the synthesizer is attempting to lock up to the reference signal.
For example, if the output from the first divider (25) is exactly 180 degrees out of phase with respect from the reference divider (34), (Such as when the synthesizer is powered up for example.), the phase detector (40) will output a signal to the VCXO (21) to go to its maximum (or minimum) output frequency needed to bring the output of the first divider (25) into phase synchronization with the reference signal from the second divider (30 and 34 together). In the circuit shown in FIG. 2, because of the limited VCXO tuning range, it will tune up (or down) by only about 5 KHz. This translates into a frequency change to the VCXO output frequency, divided by the divider (25), equal to 5 KHz .div.738,000, or about 0.00677 Hz. Since a frequency change of 1 Hz equals 360 degrees per second, the frequency range 0.00677 Hz. results in the dividers (25) output changing of 2.4 degrees per second. At this rate, assuming that the output from the first counter (25) is initially 180 degrees out of phase with respect to the output from the second counter (34), it will take 74 seconds to bring the two 100 Hz signals into phase lock.
A frequency synthesizer that is capable of providing small incremental steps in output frequency adjustment that uses a crystal controlled oscillator and a minimum number of division stages and that provides a reduced lock time would be an improvement over the prior art. In communications applications where such types of frequency synthesizers are used, many secondary benefits from reduced lock up time might be realized.